Not applicable.
The present invention generally relates to digital signal processors. More particularly, the invention relates to memory in digital signal processors. Still more particularly, the invention relates to a program memory that is shared between multiple central processing unit (CPU) cores and that can fetch instructions for multiple CPU cores in the same clock cycle.
Microprocessors generally include a variety of logic circuits fabricated on a single semiconductor chip. Such logic circuits typically include a central processing unit (CPU) core, memory, and numerous other components. Some microprocessors, such as digital signal processors (DSPs) provided by Texas Instruments, may include more than one CPU core on the same chip. For such multi-core DSP devices, typically each CPU core has an associated memory in which it stores data and program instructions. In other words, for every CPU core in a multi-core DSP device, there is a corresponding memory reserved for use by that CPU core.
It is generally desirable for microprocessors such as DSPs to be compact, consume very little power, and generate as little heat as possible. This is especially true for DSPs that reside in small, battery-powered devices such as cellular telephones, pagers, and the like. Accordingly, any improvement in DSP technology that results in smaller and lighter devices that require less power is highly desirable.
The invention disclosed may advantageously provide a compact, low power design by eliminating redundancy of on-board memory in multi-core DSP devices. In one embodiment, the multi-core DSP device has a shared program memory. As each of the program cores may execute the same software program, memory requirements may be reduced by having multiple processor cores share only a single copy of the software. Accordingly, a program memory is coupled to each of the processor cores by a corresponding instruction bus. Preferably the program memory services two or more instruction requests in each clock cycle. Data, however, is preferably stored in separate memory arrays local to the processor core subsystems. The processor cores each access their data via a dedicated data bus.
According to a preferred implementation, the program memory includes a xe2x80x9cwrapperxe2x80x9d that can perform one memory access in the first half of each clock cycle and a second memory access in the second half of the clock cycle. A designated set of instruction buses is allowed to arbitrate for only the first access, and the remaining instruction buses are allowed to arbitrate for only the second access. In this manner, a reduction in on-board memory requirements and associated power consumption advantageously may be achieved.